vllm.models.qwen4_exp.amd.ops.qsa_pre_indexer
¶
Fused QSA pre-indexer kernel for the AMD Qwen4Exp path.
Started as a copy of the NVIDIA kernel (nvidia/ops/qsa_prepare.py) and is
kept separate so either vendor can change its own copy without re-validating
the other. The state source select is two masked loads rather than a pointer
select, which ROCm Triton rejects.
Functions:
-
qsa_pre_indexer–Normalize Q, compress K, then update the circular raw state.
-
supports_fused_pre_indexer–Report whether this indexer's shapes match the fused kernel's assumptions.
_norm_rope(x, pos_t, pos_h, pos_w, cos_sin_ptr, cos_sin_stride, norm_weight_ptr, eps, IS_MROPE, MROPE_H, MROPE_W)
¶
Apply Gemma RMSNorm and selected-axis NeoX RoPE to register rows.
Source code in vllm/models/qwen4_exp/amd/ops/qsa_pre_indexer.py
qsa_pre_indexer(q, k, positions, cos_sin_cache, q_norm_weight, k_norm_weight, eps, q_out, state_cache, state_slots, state_block_table, query_start_loc, logical_positions, compressed_cache, compressed_slots, k_work_metadata, *, compress_ratio, mrope_section, rope_pos_offset)
¶
Normalize Q, compress K, then update the circular raw state.
Source code in vllm/models/qwen4_exp/amd/ops/qsa_pre_indexer.py
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supports_fused_pre_indexer(rotary_emb, head_dim, num_kv_heads, compress_ratio)
¶
Report whether this indexer's shapes match the fused kernel's assumptions.
The kernel hard-codes the rotary layout and the single-KV-head group compression it was written for; everything it rejects has a working unfused path.